1. Field of the Invention
The present invention relates to a semiconductor integrated circuit designed by a master slice or standard cell method and, more particularly, to the improvement of drawing-out of clock lines and a method of manufacturing the same.
2. Description of the Related Art
With the advance of large-scale integration of integrated circuits, the need has arisen to pay grave attention to the design of clock system. In a largescale integrated circuit, a large number of gates and flip-flops are put into operation in synchronization with a single clock signal. Thus, clock signal lines are wired all over a chip, and a large number of active elements are connected to the lines. According to such a large-scale integrated circuit, two following problems will arise.
(1) A clock driver having an extremely large current-driving capability is required in order to supply a large load with a clock signal.
(2) Noncoincident arrival of the clock signal at active elements, i.e., the clock skew occurs, causing an error in the operation timing in the integrated circuit.
Where a clock driver with great current-driving capability is formed in an integrated circuit, on one hand, a great variation in current will occur in the clock driver, switching noises will be generated locally, a supply voltage will vary, and a large amount of current will flow through the substrate. This will result in integrated circuit malfunctions. In CMOS integrated circuits in particular, there is a possibility of destruction of active elements due to latchup. On the other hand, the use of a clock driver with very great current-driving capability will increase the impedance of transmission paths. Therefore, the reduction of the clock skew cannot be expected.
To solve the above problems, there is an approach to distribute the output of the clock driver to subclock drivers and apply a clock signal to a flip-flop corresponding to each subclock driver. According to such an approach, the problem (1) can be solved in principle.
In manufacturing semiconductor devices in accordance with the polycell or master slice method, a layout work is performed for automatic placement and routing of cells. With this layout, the following method will be devised for the distribution of the clock driver output.
That is, a subclock driver cell is formed in each of cell arrays and subclock driver cells are connected to a system clock driver cell. Each subclock driver is connected to active elements, e.g. flip-flops via a signal line for application of clock pulses.
According to the above clock signal distribution method, the resistance of clock signal lines can be reduced. By thickening horizontal and vertical lines of the clock signal lines or peripheral lines, it is possible to much enhance the effect of reducing the resistance. Moreover, the above method can readily be handled by an automatic routing program. With such a clock distribution method, since the resistance component of a signal line between the system clock driver cell and each subclock driver cell is reduced, the clock skew virtually becomes negligible where the clock signal is observed at the input of each subclock driver cell. However, since the number of flip-flops connected to each subclock driver, i.e., the load of each subclock driver is not necessarily uniform, the clock skew will occur among flip-flops.
That is to say, in semiconductor integrated circuit devices formed in a layout according to an automatic placement and routing program, the clock skew due to variations in the load of the subclock drivers will be generated, resulting in causing malfunctions such as erroneous data transmission.
Such an automatic layout as described above, in which a system clock signal is divided into a plurality of subclock signals by subclock drivers, involves a problem of clock skew due to variations in the loading imposed on subclock drivers.